Take a look at the example on the right. The architecture A declares a concurrent process P which is inherited by the derived architecture A_SUB, but redefined by using the label P again.
Suppose the old process P would be hidden. It would be still active in parallel to the new process P and also be invoked in case of a change on signal Clk. Both processes would do an assignment to signal Output and because of no defined resolution function the VHDL simulator would produce an error.
So it should be clear that the old process must be overwritten in order to allow the modification of functionality.
architecture A of AN_ENTITY_E is
begin
P: process(Clk)
begin
if Clk='1' then
Output <= Input;
end if;
end process;
end A;
architecture A_SUB of AN_ENTITY_E_SUB is
new A of AN_ENTITY_E with
begin
P: process(Clk)
begin
if Clk='1' then
Output <= not Input;
end if;
end process;
end A_SUB;